Process and apparatus allowing the real-time distribution of data for control of a patterning process

ABSTRACT

A textile dyeing apparatus enables the real-time selection of destinations for pattern information. A pattern control system has a plurality of destinations for receiving pattern information. The pattern control system includes means for selecting one of the destinations in response to a selectional signal. A processor coupled to the pattern control system transfers the pattern information. The processor includes a first memory for locally storing the pattern information and a programmable direct memory access controller board, coupled to said first memory. The board initiates the transfer of the pattern information from the first memory in response to a transfer signal from the processor. The processor also includes an output data bus, receiving the transferred pattern information, coupled in parallel with the inputs of the plurality of destinations in the pattern control system, and a selection circuit providing the selection signal in real-time to the means for selecting in response to selection information stored in the first memory. &lt;IMAGE&gt;

FIELD OF THE INVENTION

This invention relates to an electronic data loading and distributionsystem and, more particularly, to a system using a programmable directmemory access controller for the real-time selection of destinations fordigitally encoded data.

The system may be used to control the selective application of dyes orother marking materials to a moving substrate in accordance withdigitally encoded pattern data. The programmable direct memory accesscontroller allows multiple patterns or repetitions of the same patternto be generated by a pattern control system across the width of thesubstrate in real-time as opposed to being generated off-line and aheadof time.

BACKGROUND OF THE INVENTION

This invention, in particular, finds application in the field of textiledyeing. A known modern textile dyeing apparatus includes multiplearrays, each comprising a plurality of individual, electronicallyaddressable dye jets. Each of the dye jets in a single array outputs thesame color of dye. The arrays are positioned in spaced relation acrossthe path of a moving substrate.

Using such apparatus, the pattern-wise application of dye to the textilematerials or substrates requires a large quantity of digitally encodedpattern data which must be sorted and routed to each of the individualdye jets comprising each of the arrays. Each of the arrays of dye jetsextends across the width of the substrate path as the substrate movesunder the arrays. It has been found advantageous to control individuallythe time period during which the dye streams produced by the individualdye jets in a given array are allowed to strike the substrate. Thisallows for shade variations to be produced from side-to-side (andend-to-end) on the substrate by varying the quantity of dye applied tothe substrate along the length of a given array.

One such control system capable of providing this capability isdescribed in co-pending U.S. Ser. No. 327,843, entitled "DATA LOADINGAND DISTRIBUTING PROCESS AND APPARATUS FOR CONTROL OF A PATTERNINGPROCESS", filed on Mar. 23, 1989, now U.S. Pat. No. 4,984,169, thespecification of which is hereby incorporated by reference. This system,which is applicable to a variety of marking or patterning systemswherein large quantities of pattern data must be allocated and deliveredto a large number of individually controllable imaging locations,processes pattern data received from a real-time processor through theuse of specific electronic circuitry which accepts the pattern data inthe form of a series of 8-bit units. Each of the 8-bit units uniquelyidentifies, for each pattern element or pixel, a pattern design elementto be associated with that pattern element or pixel.

The term "pattern element" as used herein is intended to be analogous tothe term "pixel" as that term is used in the field of electronicimaging. The number of different pattern design elements is equal to thenumber of district areas of the pattern which may be assigned a separatecolor.

The term "pattern line" as used herein is intended to describe acontinuous line of single pattern elements extending across thesubstrate, parallel to the patterning arrays. Such pattern lines have athickness, measured in the direction of substrate travel, equal to themaximum permitted amount of substrate travel under the patterning arraysbetween array pattern data updates.

In this system, the pattern element data must first be converted to"on/off" firing instructions, (referring to the actuation ordeactuation, respectively, of the individual dye streams produced by thedye jets). This is performed by electronically associating the "raw"pattern data with pre-generated firing instruction data from a computergenerated look-up table. The raw patterning data is in the form of asequence of pixel codes. The pixel codes merely define those distinctareas of the pattern which may be assigned a distinguishing color. Eachcode specifies, for each pattern line, the dye jet response for a givendye jet position on each and every array. In this system the number ofarrays equals eight; therefore, each pixel code controls the response ofeight separate dye jets (one per array) with respect to a single patternline.

The raw pattern data for a given array is preferably arranged insequence, with data for dye jets 1-N for the first pattern line beingfirst in the series, followed by data for dye jets 1-N for the secondpattern line, etc. The complete serial stream of such pixel codes issent to a firing time converter and memory associated with eachrespective array for conversion of the pixel codes into the respectivefiring times.

Each firing time converter includes a look-up table having a sufficientnumber of addresses so that each possible address code forming theserial stream of pattern data may be assigned a unique address in thelook-up table. At each address within the look-up table is a byterepresenting a relative firing time or dye contact time, which, assumingan 8-bit value at the address code of interest, can be zero or one of255 different discreet time values corresponding to the relative amountof time the dye jet in question is to remain "on". Therefore, eachspecific dye jet location on each and every array can be assigned one of256 different firing times.

The firing time data from the look-up table for each array is thenfurther processed to account for the "stagger", e.g., the physicalspacing between arrays, and the allocation of the individual firinginstructions for each jet in the array. Finally, the individual firinginstructions for each jet in the array are sent in parallel to the jetdyeing apparatus for actuation of the individual jets in each array.

These systems require a full line of pattern data to be stored in thereal-time processor memory for output to the pattern control system.When it is desired to generate different patterns or repetitions of thesame patterns across the width of the substrate, each pattern to begenerated must first be converted into a "full machine width" patternline. For example, the individual corresponding pattern lines of each ofthree separate patterns must be combined into a single set of compositepattern lines which individually extend across the entire substrate.Because this combining of pattern data into full width pattern lines isa computationally intensive process, it must be done "off-line" from theoperation of the dyeing apparatus. Further, the entire pattern must thenbe written into memory which requires an extremely large memory.

One alternative to formatting the patterns off-line and producing thepatterns in an "across the width" format would be to eliminate the "fullmachine width" conversion process and simply produce each individualpattern, in real-time, down the substrate rather than across. However,it is readily apparent that a tremendous amount of the substrate wouldthen be wasted. For example, a twelve foot wide substrate used toproduce a pattern only three feet wide, such as would be suitable for ahall or "runner" carpet, for instance, would waste the remaining ninefeet across the substrate width.

There is therefore a need for a process and apparatus which producesmultiple patterns or repetitions of the same pattern across thesubstrate in real-time. Further, the process and apparatus should becapable of producing the pattern beginning at any point along the widthof the substrate or be capable of starting the given pattern at anypoint in the pattern for proper centering of the pattern across thesubstrate and thus not delivering dye to the edges of the substrate.

SUMMARY OF THE INVENTION

The present invention overcomes these problems with the use of aprogrammable direct memory access ("DMA") controller to assist in thereal-time selection and production of multiple patterns or repetitionsof the same pattern to be generated across the substrate. The individualpattern data may be stored in separate memory locations which are thenaccessed in any desired sequence upon demand by the DMA controller. Asdiscussed above, the control system is believed to be applicable to avariety of marking or patterning systems wherein large quantities ofdifferent pattern data must be allocated and delivered to a large numberof individually controllable imaging locations, and is not limited touse in connection with the patterning devices disclosed herein.

In a preferred embodiment using the present invention, the programmableDMA controller, without intervention by the real-time processor,retrieves the same pattern data from memory a desired number of times torepeat the pattern across the width of the substrate. The DMA controlleroperates in real-time to combine the patterns into a full machine widthpattern line for output to the pattern control system. Thus, unlikesystems of the prior art, only a single copy of the pattern data need bestored in the memory to produce a repetitive number of the patterns.This results in a dramatic reduction in the size of the memoryassociated with the real-time processor used to store the pattern data.

The control system of the instant invention uses the channel selectlines provided by the DMA controller to selectively enable in real-timeone of a number of different destinations for the data output from thereal-time processor. Because of this capability, an alternate embodimentof the present invention provides for the DMA channel select lines toselect one of a plurality of look-up tables associated with each arrayin conjunction with the retrieval of different patterns from thereal-time processor memory. Thus, each pattern that is combined into thefull machine width pattern lines will have its respective correctlook-up table of firing times available when the pattern data isprocessed by the pattern control system. This allows multiple differentpatterns, or portions of a large, overall pattern (which, by dividingthe pattern into areas which individually require no more than 256pattern elements, will allow use of more than 256 pattern elements inthe overall pattern) to be produced across the width of the substrate inreal-time.

These and other advantages are provided by proper programming of thedirect memory access controller. It is thus possible to change thepattern sequences "on-line" which results in a savings in time,substrate material, and memory.

Details of the present invention herein, as well as additionaladvantages and distinguishing features, will be better understood withreference to the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating one pattern control systemenvironment in which the present invention may operate.

FIGS. 2A and 2B constitute a schematic block diagram illustrating ingreater detail the real-time computer and pattern control system of FIG.1 and, more specifically, illustrating the programmable DMA controller'sinterface with the pattern control system of FIG. 1.

FIG. 3 illustrates an example of two patterns and their associatedlook-up tables stored in the real-time computer memory.

FIGS. 4 and 4A illustrate portions of a substrate patterned inaccordance with the examples of FIG. 3.

DETAILED DESCRIPTION

For purposes of this discussion, the programmable DMA controller andcontrol system of the present invention will be described in conjunctionwith the jet patterning apparatus discussed above and to which thisinvention is particularly well suited. It should be understood, however,that the operation of the programmable DMA controller and control systemof the instant invention may be used, perhaps with obviousmodifications, in other devices where similar quantities of digitizedpattern data must be distributed in real-time to different destinations.

Referring to FIG. 1, a multiprocessor patterning system 5 is shownhaving a host computer 12 coupled via a bus 11 to a real-time computer10. Optional pattern computer 14 is further coupled to the host computer12 and real-time computer 10 by the bus 11. It is readily apparent thatthe coupling of the pattern computer 14, host computer 12 and real-timecomputer 10 may be by any means for coupling a local area network (LAN)such as an Ethernet bus.

A pattern control system 16 is coupled via bus 26 to a jet dyeingapparatus 18. The jet dyeing apparatus 18 may be of the type generallydescribed in greater detail in, for example, commonly assigned U.S. Pat.Nos. 3,894,412, 3,942,343, 3,969,779, 4,033,154, 4,034,584, 4,116,626,4,309,881, 4,434,632 and 4,584,854.

The pattern control system 16 receives inputs from bus 22 and channelselect lines 24 of the programmable DMA controller board 20. Theprogrammable DMA controller board 20 is part of the real-time computer10 and is described in greater detail in FIG. 2.

Optional pattern computer 14 may be provided to allow a user of thesystem to quickly create their own pattern design. Alternatively,pattern designs may be pre-loaded onto magnetic or optical media forreading into the system. A computer terminal 13 may be coupled via asuitable connection 17, e.g., a standard RS232 cable, to the hostcomputer 12. The terminal 13 then serves as the operator's interface forproviding the input parameters to the host computer for each "job" ofpatterns to be generated on the substrate by jet dyeing apparatus 18.The host computer 12 also fetches the pattern data from the patterncomputer or other source and sets it up for processing by the real-timecomputer 10. The real-time computer 10 functions to insure that thepattern data is properly output to the pattern control system 16 byprogramming appropriately the DMA controller board 20.

Referring to FIG. 2, the real-time computer 10 is shown having memory 34and programmable DMA controller board 20. Pattern data is received fromthe host computer 12 via the bus 11 and stored on high speed disk 33 byway of diagrammatically depicted links 35 and 35A, which typically maybe comprised of an I/O bus, associated bus interface units, and anappropriate network interface unit, not shown. As appropriate, data ismoved from high speed disk 33 into memory 34, via link 35, for access byDMA controller 20 via bus 36.

The programmable DMA controller board 20 is shown comprising aprogrammable DMA processor 32, FIFO buffer 28 and 3-bit latch 30. Theprogrammable DMA processor 32 couples with bus 36 via line 38 and withFIFO buffer 28 via line 37. Further, the 3-bit latch 30 is coupled tothe bus 36 via line 39. It should be understood that FIG. 2 shows only asimplified diagrammatically depicted version of the programmable DMAcontroller board 20. A more complete and accurate description of thecontroller board 20 can be found by consulting the specificationsthereof; for example, the controller board 20 may be of the typeproduced by Digital Equipment Corporation as Model DRQ3B or may be theIntel 82258 DMA chip used in conjunction with a host computer card suchas the Intel 286/12 Board.

Pattern numbers chosen by the operator using terminal 13 are entered vialine 17, into host computer 12 (FIG. 1). Computer 12 loads pattern datafrom, e.g., pattern computer 14, onto high speed disk 33, and then sendsdata messages to real-time computer 10. Computer 10, on receipt of suchmessages, loads the requested pattern data from high speed disk 33 intomemory 34. When requested by means of an interrupt, as by the occurrenceof a transducer pulse indicating a predetermined length of substrate haspassed under the patterning jets, the real-time computer 10 commands theDMA controller 20 to initiate the transfer of the appropriate patterndata stored in memory 34 to the pattern control system 16, via FIFObuffer 28.

In one embodiment, a first-in-first-out (FIFO) buffer 28 stores words(16-bits) of pattern data in each buffer location. The pattern datastored in FIFO buffer 28 is then output to the pattern control system 16along the high-speed (e.g., 2.6 megabytes/second) data bus 22. The FIFObuffer 28 serves as an interface between the rate at which data isplaced into the FIFO buffer 28 by DMA processor 32 and the rate at whichdata is output to the pattern control system 16. If the pattern controlsystem 16 operates at a rate equal to or greater than that of thereal-time processor 10, FIFO buffer 28 would not be needed to performthe interface function.

In accordance with commands from the real-time computer 10, the DMAprocessor 32 also functions to request memory 34 to provide inputs vialine 39 to the 3-bit latch 30. The latch 30 provides a parallel outputon the three channel select lines 24 to the pattern control system 16.

The demultiplexer 42 receives the channel select lines 24 and providesone of eight outputs depending upon the state of the channel selectlines 24. The demultiplexer 42 may be any suitable conventional 3-to-8type demultiplexer.

A portion of the pattern control system 16 is shown in FIG. 2 having a3:8 demultiplexer 42, a series of 16-bit registers, and a 16-to-8 bitdata multiplexer 40.

Multiplexer 40 receives the 16-bit words (when either the pattern dataselect line 45 or the LUT load data select line 47 is selected by thechannel select lines 24, through demultiplexer 42) over data bus 22 fromthe FIFO buffer 28 in the programmable DMA controller board 20. The16-bit multiplexer 40 then provides single byte (8 bit) write outputsover 8-bit bus 44. Therefore, the data multiplexer 40 serves to converteach 16-bit parallel word into a sequence of two bytes over 8-bitparallel bus 44 for pattern data or LUT load data. The bus 44 is furthercoupled in parallel with an array of N firing time converters (numbers 1through N), each firing time converter corresponding to one of N arraysof individual dye jets. Each firing time converter 1 though N includes aplurality of look-up tables (LUT arrays 1 through N) addressed by thecontents of the LUT select register 46 which provides the upper addresslines to each firing time converter array. Each firing time converterarray may be thought of as a simple high speed static memory havingaddress lines, data-in lines, data-out lines, and read and write controllines.

The other four 16-bit registers can be loaded by selecting theappropriate register with the channel select lines and providing thedesired value on 16-bit bus 22.

One of the four 16-bit registers loaded by bus 22 is the look-up table(LUT) select register 46. In the embodiment shown in FIG. 2, 9 bits fromthe LUT select register provide the upper nine address lines to each LUTarray (1 through N), thus providing 512 LUTs for each respective array.For purposes of discussion, this embodiment is assumed to include 8arrays (N=8) and, as mentioned above, 512 LUTs per array. Each look-uptable has a sufficient number of addresses so that each possible addresscode forming the serial stream of pattern data may be assigned a uniqueaddress in each of the look-up tables. At each address within thelook-up table is a byte representing a relative firing time or dyecontact time. Assuming an 8 bit address code used to form the rawpattern data, the firing time can be zero or one of 255 differentdiscrete time values corresponding to the relative amount of time thedye jet in question is to remain "on". Accordingly, for each 8 bit byteof pixel data, one of 256 different firing times (including a firingtime of zero) is defined for each specific jet location on each andevery array 1-N. Jet identity within a given array is determined by therelative position of the address code within the serial stream ofpattern data and by the information pre-loaded into the look-up tables,which information specifies in which arrays a given jet position fires,and for what length of time.

The 8-bit bus 44 from DATA MUX 40 is connected in parallel to the datainputs of the firing time converters. It is also connected to the inputof MUX 48. Connected to the other input of MUX 48 is AUTO addressgenerator 50. Depending on the state of channel select lines 24, one orthe other of these inputs can be connected to the lower address lines ofeach LUT array. To load an array with conversion data, select lines 24activate the LUT load data select line 47. This "enables" DATA MUX 40,as well as connects AUTO address generator 50 through MUX 48 to thelower address lines of each LUT array in sequence, and provides asequential "write enable" through sequencer 52 to each LUT within eachLUT array selected by LUT select register 46 for each LUT array. (Thefirst 256 bytes on bus 44 are loaded into LUT array 1; the second 256bytes are loaded into LUT array 2, etc.)

To output pattern data through the LUT's, select lines 24 activate thepattern data select line 45, which "enables" DATA MUX 40, routes data onbus 44 through MUX 48 to the lower address lines of each LUT array, andprovides a "read enable" signal to each LUT array such that data frombus 44 selects the appropriate contents (i.e., firing time) of each LUTselected by the LUT select register 46. This firing time is output onits respective data out bus 55 to each stagger memory array 56. Thus,depending upon the output from channel select lines 24 of theprogrammable DMA controller 20, the enabling of one of the eightpossible output lines from demultiplexer 42 directs where data from bus22 will go (i.e., to one of the 16 bit registers, or through DATA MUX 40to the data inputs of the LUT arrays, or channeled through MUX 48 to thelower address lines of each LUT array).

The firing time information from the LUT arrays comprising firing timeconverters 1-N is supplied to a respective stagger memory 56 for each ofthe LUT arrays 1-N. The stagger memories 56 1-N function to compensatefor the time necessary for the substrate to be patterned to travel fromarray to array due to the physical spacing between the arrays in the jetdyeing apparatus. The stagger memory 56 operates on the firing time dataproduced by LUT arrays 54 and performs two principal functions: (1) theserial data stream from the LUT array, representing firing times, isgrouped and allocated to the appropriate arrays on the patterningmachine and (2) "non-operative" data is added to the respective patterndata for each array to inhibit, at start up and for a predeterminedinterval which is specific to that particular array, the reading of thepattern data in order to compensate for the elapsed time during whichthe specific portion of the substrate to be patterned with that patterndata is moving from array to array. The precise operation of thestaggered memories is described fully in co-pending Ser. No. 327,843referenced above.

The stagger memories 56 provide their output to a "Gatling" memorymodule 58 for each array. The Gatling memory 58 performs two principalfunctions: (1) the serial stream of encoded firing times is converted toindividual strings of logical (i.e., "on" or "off") firing commands, thelength of each respective "on" string reflecting the value of thecorresponding encoded firing time, and (2) these commands are quicklyand efficiently allocated to the appropriate dye jets. Thus, the Gatlingmemory arrays serve to distribute the encoded firing times to theappropriate jets for each dye jet array such that the desired pattern isproduced on the substrate moving under the dye jet arrays. Again, asnoted above, a complete description of the Gatling memory modules isprovided in co-pending Ser. No. 327,843.

It is readily apparent that because the DMA controller can be programmedto change the channel select lines 24 in real-time, it is possible toenable different look-up tables in each of the arrays by reloading LUTselect register 46 in real-time between pattern data outputs, for theprocessing of different pattern data across the width of the substrate.This allows multiple (different or identical) patterns to be printedside-by-side in real-time, each with its own look-up table of firingtimes.

An example showing a typical use of this system is now described below,in which two different patterns are produced across the substrate usingthe programmable DMA controller 20.

FIG. 3 is an example showing PATTERN A and PATTERN B as they exist inmemory 34 (FIG. 2). Also shown are look-up tables A and B as they existin memory 34. Real-time computer 10 loads these items in memory 34 priorto the time that they are actually needed. FIG.4 illustrates thefinished product or pattern of producing one repeat of PATTERN A and tworepeats of PATTERN B on the substrate.

Referring again to the example of FIG. 3, PATTERN A is shown being sixpixels wide by five pattern lines long. It is arranged in memory 34 as asequence of 30 contiguous bytes as indicated by the relative address (inmemory numbers) in the upper right portion of the cells. This patterncontains two different pattern elements numbered "10" and "20". Theseare two independent areas of the pattern which will generate twodifferent colors on the final product. The look-up table for PATTERN A(LUT A) serves to translate the PATTERN A elements into firing timeinformation for each dye jet array.

Note that element 10 translates to firing time 22 (typically inmilliseconds) for the RED ARRAY and element 20 translates to firing time22 for the BLUE ARRAY. This means that area 10 will be RED on the finalsubstrate and area 20 will be BLUE. Firing time 22 is a relative amountof time to deliver dye from the dye jets which is directly proportionalto the amount of dye delivered. PATTERN B and its associated look-uptable LUT B will be translated in a similar manner to PATTERN A. Thefinished product will be as shown in FIG. 4.

A sequence of DMA commands for producing the product of FIG. 4 is givenin Table 1 below. Real-time computer 10 sets up these commands in memoryand instructs DMA controller 20 to execute them at the appropriate time.The appropriate time is determined by means of an interrupt such as atransducer pulse occurring after a predetermined length of substrate hastravelled under the jet dyeing apparatus for each pattern line.

                  TABLE 1                                                         ______________________________________                                        Line 0 Group 1                                                                          SET CHANNEL SELECT LINES =                                                    LUT SELECT                                                                    OUTPUT LUT NUMBER = 1                                                         WAIT ON FIFO EMPTY                                                  Line 0 Group 2                                                                          SET CHANNEL SELECT LINES =                                                    LUT LOAD                                                                      OUTPUT LUT A                                                                  WAIT ON FIFO EMPTY                                                  Line 0 Group 3                                                                          SET CHANNEL SELECT LINES =                                                    LUT SELECT                                                                    OUTPUT LUT NUMBER = 0                                                         WAIT ON FIFO EMPTY                                                  Line 0 Group 4                                                                          SET CHANNEL SELECT LINES =                                                    PATTERN DATA                                                                  OUTPUT LAST LINE OF PREVIOUS                                                  PATTERN                                                             Line 1 Group 1                                                                          SET CHANNEL SELECT LINES =                                                    LUT SELECT                                                                    OUTPUT LUT NUMBER = 2                                                         WAIT ON FIFO EMPTY                                                  Line 1 Group 2                                                                          SET CHANNEL SELECT LINES =                                                    LUT LOAD                                                                      OUTPUT LUT B                                                                  WAIT ON FIFO EMPTY                                                  Line 1 Group 3                                                                          SET CHANNEL SELECT LINES =                                                    LUT SELECT                                                                    OUTPUT LUT NUMBER = 1                                                         WAIT ON FIFO EMPTY                                                  Line 1 Group 4                                                                          SET CHANNEL SELECT LINES =                                                    PATTERN DATA                                                                  OUTPUT 2 BYTES = 255                                                          OUTPUT FIRST LINE OF PATTERN A (6                                             BYTES)                                                                        OUTPUT 2 BYTES = 255                                                          WAIT ON FIFO EMPTY                                                  Line 1 Group 5                                                                          SET CHANNEL SELECT LINES =                                                    LUT SELECT                                                                    OUTPUT LUT NUMBER = 2                                                         WAIT ON FIFO EMPTY                                                  Line 1 Group 6                                                                          SET CHANNEL SELECT LINES =                                                    PATTERN DATA                                                                  OUTPUT FIRST LINE OF PATTERN B (4                                             BYTES)                                                                        OUTPUT FIRST LINE OF PATTERN B (4                                             BYTES)                                                                        OUTPUT 2 BYTES = 255                                                Line 2 Group 1                                                                          SET CHANNEL SELECT LINES =                                                    LUT SELECT                                                                    OUTPUT LUT NUMBER = 1                                                         WAIT ON FIFO EMPTY                                                  Line 2 Group 2                                                                          SET CHANNEL SELECT LINES =                                                    PATTERN DATA                                                                  OUTPUT 2 BYTES = 255                                                          OUTPUT SECOND LINE OF PATTERN A                                               (6 BYTES)                                                                     OUTPUT 2 BYTES = 255                                                Line 2 Group 3                                                                          SET CHANNEL SELECT LINES =                                                    LUT SELECT                                                                    OUTPUT LUT NUMBER = 2                                                         WAIT ON FIFO EMPTY                                                  Line 2 Group 4                                                                          SET CHANNEL SELECT LINES =                                                    PATTERN DATE                                                                  OUTPUT SECOND LINE OF PATTERN B                                               (4 BYTES)                                                                     OUTPUT SECOND LINE OF PATTERN B                                               (4 BYTES)                                                                     OUTPUT 2 BYTES = 255                                                Line 3    SAME AS LINE 2 EXCEPT THIRD LINE                                              OF PATTERNS A & B OUTPUT                                            Line 4    SAME AS LINE 2 EXCEPT FOURTH LINE                                             OF PATTERN A OUTPUT AND FIRST                                                 LINE OF PATTERN B OUTPUT                                            Line 5    SAME AS LINE 2 EXCEPT FIFTH LINE                                              OF PATTERN A OUTPUT AND SECOND                                                LINE OF PATTERN B OUTPUT                                            ______________________________________                                    

Line 0 must occur sometime prior to line 1. In this example, it will bethe last pattern line of the previous pattern. The first command inGroup 1 for line 0, SET CHANNEL SELECT LINES=LUT SELECT, provides anoutput on channel select lines 24 to the demultiplexer 42 which signalsthe write enable line "LUT SELECT" coupled to LUT select register 46.The next command, OUTPUT LUT NUMBER=1, instructs the DMA controllerboard 20 to provide as an output on bus 22 a word of data (16 bits withonly 9 bits used in this embodiment) equal to 1, which identifies thelook-up table number to the LUT select register 46. The look-up tableselect register 46 selects, via bus 49, the correct look-up table in therespective firing time converters 1-N 54, in accordance with the look-uptable number, that will be used in succeeding operations.

The third command, WAIT ON FIFO EMPTY, is provided to allow the FIFOBUFFER 28 to be emptied prior to changing the channel select lines 24.This insures that all data meant to go to the LUT select register 46 hasbeen distributed. It is readily apparent that this command would not benecessary if the FIFO 28 were not in the system. For the presentembodiment, this command instructs the DMA controller 20 to read its ownstatus register and mask (not shown), and compare it to determine when aFIFO empty bit becomes set, and then proceed to the next command when amatch is detected.

The first command in Group 2, SET CHANNEL SELECT LINES =LUT LOAD,enables the LUT LOAD DATA SELECT line 47 from demultiplexer 42 which iscoupled to DATA MUX 40, WRITE SEQUENCER 52 and MUX 48. This enables thenext command, OUTPUT LUT A, to provide the firing time data contained inLUT A as shown in FIG. 3 on bus 44 to load the selected look-up table(in this case LUT 1) in each array sequentially as controlled by AUTOADDRESS generator 50 and WRITE SEQUENCER 52. Again, a WAIT ON FIFO EMPTYcommand is included to allow the FIFO buffer 28 to empty before changingthe channel select lines 24. These commands essentially load LUT A intoLUT 1 in firing time convertors 1-N 54.

The first command in Group 3, SET CHANNEL SELECT LINES=LUT SELECT,provides an output on channel select lines 24 to the demultiplexer 42which signals the write enable line, LUT SELECT, coupled to LUT selectregister 46. The next command, OUTPUT LUT NUMBER=0, instructs the DMAcontroller board 20 to provide as an output 0 on bus 22. This number iswritten into LUT select register 46. Again, a WAIT ON FIFO EMPTY commandis included to allow the FIFO buffer 28 to empty before changing thechannel select lines 24. These commands essentially connect LUT 0 forsubsequent operations.

The first command in Group 4, SET CHANNEL SELECT LINES=PATTERN DATA,changes the channel select lines 24 such that demultiplexer 42 assertsthe PATTERN DATA select line 45. This enables data from bus 44 to beinput on the lower address lines for the firing time converters suchthat each pattern element translates in parallel to the appropriatefiring time for each array through firing time convertors 1-N 54 for LUT0 as selected above. Finally, the command, OUTPUT LAST LINE OF PREVIOUSPATTERN, sends the pattern data fetched from real-time computer memory34 through the enabled DATA MUX 40 to be output on bus 44 through MUX48, to the lower address lines of the firing time converters 1-N. Thepattern data output on bus 44 is a serial stream of 8-bit patternelements which act as addresses for the selected LUT (0) in each array1-N. The parallel output from firing time converters 1-N 55 drivesstagger memories 56 which output data on bus 57 which drives Gatlingmemories 58 which finally activates the appropriate dye jets in each dyejet array for the specified times for the appropriate line of data.

Once the LUT A is loaded into LUT 1 in the firing time convertors 1-N54, the system is ready to output LINE 1 of PATTERN's A and B (FIG. 3).The first command of Group 1 for line 1, SET CHANNEL SELECT LINES=LUTSELECT, provides an output on channel select lines 24 to thedemultiplexer 42 which signals the write enable line LUT SELECT coupledto LUT select register 46. The next command, OUTPUT LUT NUMBER=2,identifies the look-up table number to the LUT select register 46. Thelook-up table select register 46 selects, via bus 49, the correctlook-up table in the respective firing time convertors 1-N 54, inaccordance with the look-up table number, that will be used insucceeding operations. The third command, WAIT ON FIFO EMPTY, isprovided to allow the FIFO BUFFER 28 to be emptied prior to changing thechannel select lines 24.

The first command in Group 2 for Line 1, SET CHANNEL SELECT LINES=LUTLOAD, enables the LUT LOAD data select line 47 from demultiplexer 42which is coupled to DATA MUX 40, WRITE SEQUENCER 52 and MUX 48. Thisenables the next command, OUTPUT LUT B, to provide the firing time datacontained in LUT B as shown in FIG. 3 on bus 44 to load the selectedlook-up table (in this case LUT 2) in each array sequentially ascontrolled by AUTO ADDRESS generator 50 and WRITE SEQUENCER 52. Again, aWAIT ON FIFO EMPTY command is included to allow the FIFO buffer 28 toempty before changing the channel select lines 24. These commandsessentially load LUT B into LUT 2 in firing time converters 1-N 54.

The first command in Group 3 for Line 1, SET CHANNEL SELECT LINES=LUTSELECT, provides an output on channel select lines 24 to thedemultiplexer 42 which signals the write enable line LUT SELECT coupledto LUT select register 46. The next command, OUTPUT LUT NUMBER=1,instructs the DMA controller board 20 to provide as an output 1 on bus22. This number is written into LUT select register 46. Again, a WAIT ONFIFO EMPTY command is included to allow the FIFO buffer 28 to emptybefore changing the channel select lines 24. These commands essentiallyconnect LUT 1 for subsequent operations.

The first command in Group 4 for Line 1, SET CHANNEL SELECTLINES=PATTERN DATA, changes the channel select lines such thatdemultiplexer 42 asserts the PATTERN DATA select line 45. This enablesdata from bus 44 to be input on the lower address lines for the firingtime converters such that each pattern element translates in parallel tothe appropriate firing time for each array through firing timeconverters 1-N 54 for LUT 1 loaded with LUT A (FIG. 3) above. The nextcommand, OUTPUT 2 BYTES=255, sends two bytes equal to 255 (an elementwhich translates to zero firing time for all dye jet arrays) fromreal-time computer memory 34 through the enabled DATA MUX 40 to beoutput on bus 44 through MUX 48, to the lower address lines of thefiring time converters 1-N. These two bytes will essentially assure nodye on the left edge of the final product as shown in FIG. 4. The nextcommand, OUTPUT FIRST LINE OF PATTERN A (6 BYTES), sends the first 6bytes of PATTERN A (10, 10, 20, 20, 10, 10) from real-time computermemory 34 through the enabled DATA MUX 40 to be output on bus 44 throughMUX 48, to the lower address lines of the firing time converters 1-N 54.The resulting looked up firing time information will be 22, 22, 0, 0,22, 22 for array 1 and 0, 0, 22, 22, 0, 0 for array 3. All remainingarrays include all zeroes. The next command, OUTPUT 2 BYTES=255, sendstwo bytes equal to 255 (an element which translates to zero firing timefor all dye jet arrays) from real-time computer memory 34 through theenabled DATA MUX 40 to be output on bus 44 through MUX 48, to the loweraddress lines of the firing time converters 1-N. These two bytes willessentially assure no dye between PATTERN A and the two repeats ofPATTERN B as shown in FIG. 4. Again, a WAIT ON FIFO EMPTY command isincluded to allow the FIFO buffer 28 to empty before changing thechannel select lines 24.

The first command in Group 5 for Line 1, SET CHANNEL SELECT LINES=LUTSELECT, provides an output on channel select lines 24 to thedemultiplexer 42 which signals the write enable line LUT SELECT coupledto LUT select register 46. The next command, OUTPUT LUT NUMBER=2,instructs the DMA controller board 20 to provide as an output 2 on bus22. This number is written into LUT select register 46. Again, a WAIT ONFIFO EMPTY command is included to allow the FIFO buffer 28 to emptybefore changing the channel select lines 24. These commands essentiallyconnect LUT 2 for subsequent operations.

The first command in Group 6 for Line 1, SET CHANNEL SELECTLINES=PATTERN DATA, changes the channel select lines such thatdemultiplexer 42 asserts the PATTERN DATA select line 45. This enablesdata from bus 44 to be the lower address lines for the firing timeconverters such that each pattern element translates in parallel to theappropriate firing time for each array through firing time converters1-N 54 for LUT 2 loaded with LUT B (FIG. 3) above. The next command,OUTPUT FIRST LINE 0F PATTERN B (4 BYTES), sends the first 4 bytes ofPATTERN B (16, 92, 92, 16) from real-time computer memory 34 through theenabled DATA MUX 40 to be output on bus 44 through MUX 48, to the loweraddress lines of the firing time converters 1-N 54. The resulting lookedup firing time information will be 36, 0, 0, 36 for array 1 and 0, 44,44, 0 for array 7 and all zeroes for the remaining arrays. This commandessentially produces the first line of the first repeat of PATTERN B.The next command, OUTPUT FIRST LINE OF PATTERN B (4 BYTES), essentiallydoes the same as the last command and produces the second repeat ofPATTERN B on the substrate. The next command, OUTPUT 2 BYTES=255, sendstwo bytes equal to 255 (an element which translates to zero firing timefor all dye jet arrays) from real-time computer memory 34 through theenabled DATA MUX 40 to be output on bus 44 through MUX 48, to the loweraddress lines of the firing time converters 1-N. These two bytes willessentially assure no dye on the right side of the substrate as shown inFIG. 4. This completes all of the commands necessary to produce thefirst line of the final product.

The series of commands for Line 2 are essentially the same as Groups 3-6for Line 1 except that the second line for PATTERNs A and B areoutputted. The series of commands for Line 3 are essentially the same asfor Line 2 except that the third line for PATTERNs A and B areoutputted. The series of commands for Line 4 are essentially the same asfor Line 2 except that the fourth line of PATTERN A and the first lineof PATTERN B is outputted. The series of commands for Line 5 areessentially the same as for Line 2 except that the fifth line of PATTERNA and the second line of PATTERN B are outputted. It should beunderstood that the above example illustrates how to repeat a pattern ina lengthwise direction. As noted with respect to line 4, PATTERN Bbegins starting over in the lengthwise direction.

It is readily apparent from this example that a single full widthpattern may be produced on the substrate or multiple independentpatterns may be produced across the substrate and any pattern may berepeated across the substrate to fill the desired width for thatpattern. This is shown in FIG. 4A. It is also apparent that the patternsmay be shifted, expanded, or contracted depending upon how many bytesequal to 255 are outputted at the beginning and end of each line ofpattern data. Note also that for proper pattern registration, repeats ofthe patterns may begin in the middle of a pattern, go to the end, thenstart at the beginning for full repeats, and then end up with a partialrepeat on the other side. The programmable DMA controller board inconjunction with the use of the channel select lines makes flexiblepatterning possible.

Overall, the use of the programmable direct memory access controller ofthe present invention provides for the real-time functioning of thepatterning apparatus. The DMA controller provides increased flexibilitywith respect to changing the pattern sequences on-line. Further, bybeing able to repeatedly access pattern data from memory, there is asubstantial savings in memory space for the real-time processor. By thistechnique, far less memory is required, and the data necessary toproduce a full width line of patterns can be generated much more quicklyand in real-time, as opposed to off-line.

What is claimed is:
 1. A textile dyeing apparatus enabling the real-timeselection of destinations for pattern information, comprising:a) apattern control system having a plurality of destinations for receivingpattern information, said pattern control system further including meansfor selecting one of said destinations in response to a selectionalsignal; b) a processor coupled to the pattern control system fortransferring the pattern information, said processor comprising:i) afirst memory for locally storing said pattern information; and ii) aprogrammable direct memory access controller board, coupled to saidfirst memory for initiating the transfer of the pattern information fromthe first memory in response to a transfer signal from the processor,including an output data bus, receiving the transferred patterninformation, coupled in parallel with the inputs of the plurality ofdestinations in the pattern control system, and a selection circuitproviding the selection signal in real-time to the means for selectingin response to selection information stored in the first memory.
 2. Atextile dyeing apparatus according to claim 1 wherein the programmabledirect memory access board further comprises:a DMA processor coupled tothe first memory and the output data bus, operable in response to DMAcommands stored in the first memory, to access the pattern informationand selection information; and wherein said selection circuit comprisesa second memory for receiving and storing the selection information fromthe first memory and enabling a plurality of selection lines coupled tothe means for selecting.
 3. A textile dyeing apparatus according toclaim 2, which further comprises a third memory having an address line,data input line, data output line, read control line and write controlline and is coupled to said output data bus.
 4. A textile dyeingapparatus according to claim 3, which further comprises a compensatingmemory, coupled to said third memory, which contains compensating dataand which received firing times and modifies said times in accordancewith said compensating data to compensate for individual applicatorcharacteristics.
 5. A textile dyeing apparatus according to claim 4,which further comprises a fourth memory, coupled to said compensatingmemory, which accepts a serial stream of firing times from saidcompensating memory and appropriates said firing times to a plurality ofindividual dye jets.
 6. A textile dyeing apparatus according to claim 3,wherein said second memory further comprises aFirst-In-First-Out-Memory.
 7. A textile dyeing apparatus according toclaim 3, wherein said second memory further comprises a latch means. 8.A textile dyeing apparatus according to claim 7, wherein said latchmeans is coupled to a means for demultiplexing data.
 9. A textile dyeingapparatus according to claim 8, wherein said write control lines arecoupled to a write sequencing means.
 10. A textile dyeing apparatusaccording to claim 9, wherein said write sequencing means is connectedto said means for demultiplexing data.
 11. A textile dyeing apparatusaccording to claim 6, further comprising a data multiplexing meanscoupled to said First-In-First-Out-Memory and said data input line. 12.A textile dyeing apparatus according to claim 6, further comprising aselection register means coupled to said First-In-First-Out-Memory andsaid address line.
 13. A textile dyeing apparatus according to claim 10,further comprising a multiplexing means coupled to a data multiplexingmeans and said means for demultiplexing data and said address line. 14.A textile dyeing apparatus according to claim 13, wherein said datamultiplexing means is coupled to said First-In-First-Out-Memory and saiddata input line.
 15. A textile dyeing apparatus according to claim 13,further comprising an auto address generating means coupled to saidmultiplexing means.
 16. A method for enabling the real-time selection ofdestinations for pattern information for textile dyeing, comprising:a.receiving pattern information from a pattern control system having aplurality of destinations; b. selecting one of said destinations inresponse to a selectional signal; c. transferring pattern informationfrom a first memory to a programmable direct access memory controllerboard; d. receiving the transferred pattern information by the inputs ofsaid destinations; and e. repeating, in sequence, steps (a) through (d)in iterative fashion until all pattern lines have been processed. 17.The method of claim 16, which further comprises a step of accessingpattern information and selection information by use of DMA processorcoupled to said first memory.
 18. The method of claim 17, which furthercomprises a step of receiving selection information from said firstmemory.
 19. The method of claim 18, which further comprises a step ofstoring selection information from said first memory into a secondmemory.
 20. The method of claim 19, which further comprises a step oftransmitting data to a third memory having an address line, data inputline, data output line, read control line and write control line priorto said step of receiving the transferred pattern information by theinputs of said destinations.
 21. The method of claim 20, which furthercomprises a step of processing data by a first data multiplexing meansprior to said step of transmitting data to a third memory.
 22. Themethod of claim 21, wherein said step of selecting one of saiddestinations in response to a selection signal further comprises a stepof transmitting selection data from said second memory followed by astep of demultiplexing data by a demultiplexing means prior to the stepof transmitting data to said third memory.
 23. The method of claim 21,wherein said step of selecting one of said destinations in response to aselection signal further comprises a step of transmitting selection datafrom said second memory followed by a step of storing data by aselection register means prior to the step of transmitting data to saidthird memory.
 24. The method of claim 23, which further comprises a stepof transmitting data to the write control line of said third memoryfollowing the step of demultiplexing data by a demultiplexing means. 25.The method of claim 24, which further comprises a step of transmittingdata to said address line of said third memory following the step ofdemultiplexing data by a demultiplexing means.
 26. The method of claim25, wherein said step of transmitting data to said address line of saidthird memory utilizes pattern information, selection information andautomatically generated addresses which are then processed by a seconddata multiplexing means.